A probe apparatus is an apparatus for testing electrical characteristics of all semiconductor chips formed on a semiconductor wafer. Generally, the probe apparatus includes a loader chamber for transferring a semiconductor wafer and a prober chamber for testing the electrical characteristics of the semiconductor wafer transferred from the loader chamber.
The prober chamber has a movable wafer chuck for holding the semiconductor wafer, a probe card provided above the wafer chuck, and an alignment mechanism for aligning a plurality of probes of the probe card with a plurality of electrode pads of each of the semiconductor chips formed on the semiconductor wafer held by the wafer chuck. A head plate is provided on a top surface of the probe chamber, and a test head connected to a tester is disposed on the head plate. The tester tests the electrical characteristics of the test head and the semiconductor chips in electrical contact with the probe card.
In recent development of semiconductor devices, high-density and miniaturized wiring structures of semiconductor chips are adopted. Further, a diameter of a semiconductor wafer is increased in order to improve a production yield of the semiconductor chips. Therefore, a probe card is scaled up, and a density of probes is increased. Moreover, a plurality of semiconductor chips needs to be tested simultaneously.
In order to test the electrical characteristics of the semiconductor chips by using the probe apparatus, a semiconductor wafer W held by a wafer chuck 1 is aligned with probes 2 of a probe card and, then, the wafer chuck 1 is raised to bring the electrode pads of the semiconductor chips into contact with the probes 2, as shown in FIG. 9A. Next, the wafer chuck 1 is overdriven, and the probes 2 come into tight contacts with the electrode pads P while scratching the oxide film. Accordingly, the probes 2 are brought into electrical contact with the electrode pads P, and the electrical characteristic test is carried out.
Due to the scaling-up and the high-density of the semiconductor wafer W, when the probes 2 are brought into electrical contact with the electrode pads P of the semiconductor chips formed in the outer circumferential portion of the semiconductor wafer W, the wafer chuck 1 is inclined by an eccentric load applied from the probes 2 to the semiconductor chips. Hence, the right and the left probe 2 are excessively misaligned to respective dashed line positions by an amount of b μm, as illustrated in FIG. 9A. The right probe 2 is misaligned from a solid line position to a dashed line position by an amount larger than a proper misalignment amount, i.e., a μm+b μm, and leaves a deep needle trace, and the left probe 2 is misaligned from a solid line position to a dashed line position by an amount smaller than the proper misalignment amount, i.e., a μm−b μm, and leaves a shallow needle trace, as illustrated in FIGS. 9A and 9B. As the semiconductor wafer W is scaled up, this phenomenon becomes more evident. Accordingly, one of the probes 2 inflicts damages on the electrode pad P, whereas the other probe 2 is not brought into electrical contact with the electrode pad P due to the shallow needle trace.
To that end, the present inventors proposed a probe method capable of solving the above drawbacks in Japanese Patent Application Publication No. H11-30651 and its corresponding U.S. Pat. No. 6,297,656. In this probe method, the inclination of the wafer chuck 1 is calculated in advance, and the excessive misalignment is prevented by moving the wafer chuck 1 in X, Y and Z directions such that the wafer chuck 1 is ultimately inclined in a direction indicated by an arrow of FIG. 10A which is opposite to the direction in which the wafer chuck 1 is inclined when the electrode pads P and the probes 2 are in electrical contact with each other as shown in FIG. 10A. If the inclination of the wafer chuck 1 is corrected by this probe method, the misalignment amounts of the right and the left probe 2 can be controlled to the proper level, i.e., a μm, as shown in FIGS. 10B and 10C, so that the highly reliable electrical characteristic test can be performed.
In addition, a method for correcting inclination of a wafer chuck is disclosed in Japanese Patent Application Publication No. H10-150081.
The conventional wafer chuck inclination correcting method described in Japanese Patent Application Publication Nos. H11-30651 and H10-150081 are effective in testing semiconductor chips formed in the outer circumferential portion of the semiconductor wafer W held by the wafer chuck 1. However, the conventional inclination correcting methods cannot correct the inclination of the wafer chuck 1 in the case of using a probe card having a size which can be brought into contact with all the semiconductor chips of the semiconductor wafer simultaneously.